1. Field of the Invention
The present invention relates to a semiconductor device of the LOC (lead on chip) structure type having a flexible wiring pattern, and a making method for the same.
2. Description of the Related Art
The LOC structure is intended to fix leads-provided insulating tapes to the electrode-pads-arranged main surface of a semiconductor chip. The leads are electrically connected to their corresponding electrode pads. This enables a package to be made smaller in size.
FIGS. 1 through 3 are plan views showing the method of making the conventional semiconductor device of the LOC structure type, and this making method is carried out in the order as shown in FIGS. 1, 2 and 3. FIGS. 4 through 6 are sectional views showing the semiconductor device made as shown in FIGS. 1 through 3. FIGS. 4, 5 and 6 correspond, in this case, to FIGS. 1, 2 and 3, respectively. Leads 11 shown in FIGS. 1 through 6 are connected to lead frames (not shown) at their outer ends. Reference numeral 31 represents a support used when the punching process is conducted. As shown in FIGS. 2 and 5, insulating tapes 2 are bonded to those end portions of the leads 11 which are bonded to the top surface of the semiconductor chip by the insulating tapes 2. The inner leads 11 are then connected to electrode pads 4 by bonding wires 5, as shown in FIGS. 3 and 6.
When the semiconductor device has the above-described arrangement of its components, however, some problems are caused in making it. The step of bonding the tapes to the leads is carried out after the leads 11 are punched by a pressing machine. Therefore, at least all of one ends of the leads 11 must be connected to lead frames or outer frames. This limits the designing freedom of inner lead pattern. In other words, the leads cannot meet the need of forming a wiring pattern which can be used instead of or to assist metal wirings formed on the semiconductor chip. In short, the leads cannot be formed independent of the others on each of the tapes. When they can be formed so, it is more advantageous and desirable in advancing the semiconductor device into multi-chip one. Further, each tape must have a bonding margin Ad when it is bonded to one ends of the leads. This also limits the designing freedom of inner lead pattern.
In the conventional semiconductor device of the LOC structure type, therefore, the leads cannot be formed independent of the others on the tapes and this limits the designing freedom of inner lead pattern. In addition, it is difficult to use the inner lead pattern as wirings between the semiconductor chip and the leads.